Low Power Double Edge Pulse Triggered Flip Flop Design

In this paper a novel low power double edge pulse triggered flip flop (FF) design is present. First, the pulse generation control logic by using the NAND function and is removed from the critical path to facilitate a faster discharge operation. A simple two transistor NAND gate design is used to reduce the circuit complexity. Second, a double edge conditional discharging flip flop is used to reduce the switching activity and also the different techniques are there to reduce. As a result, transistor sizes in delay inverter and pulse-generator circuit can be reduced for power saving, Various simulation results based on CMOS 90-nm technology reveal that the Double edge modified hybrid latch flip flop design features the best power-delay-product performance in several FF design under comparison. Its maximum power saving design is up to 38.4%. Compared with the conversional transmission gate based flip flop design.